1. Field of the Invention
The present invention relates to an apparatus and method for testing reliability of a trench-type device isolation insulating film of a semiconductor device.
2. Description of the Related Art
In semiconductor devices such as a nonvolatile memory, in which a large number of elements are formed and arrayed on a semiconductor substrate, a trench-type device isolation insulating film, e.g., a shallow trench isolation (STI) film is provided to insulate and isolate the elements from one another. The trench-type device isolation insulating film is formed by forming trenches in a semiconductor substrate to a predetermined depth and by filling the trenches with insulating films. For example, FIG. 3 is a block diagram showing a flash memory with a memory cell array MA in which a large number of memory cells M are arranged in a matrix. The memory cells M arranged in a row direction are connected with a control gate CG as a word line WL extending in the row direction. The memory cells M arranged in a column direction are connected with a bit line BL extending in the column direction. The word lines WL are connected to a word decoder WD, which selects one of the word lines based on a row address. Similarly, the bit lines BL are connected to a bit decoder BD, which selects one of the bit lines based on a column address.
FIGS. 1A and 1B are schematic cross sectional views showing the memory cells M of the flash memory. Specifically, FIG. 1A is a cross sectional view of the memory cells arranged in the row direction, and FIG. 1B is a cross sectional view of the memory cells arranged in the column direction. Trenches 106 are formed in a predetermined pitch in the row direction in the surface portion of a well WELL formed in a semiconductor substrate 101. Drain regions D 109 and source regions S 110 are formed in the surface portion of the well WELL between the trenches 106. In addition, a tunnel oxide film 102 is formed on the surface of the well WELL, and a floating gate film 103 as a floating gate FG is formed on the tunnel oxide film 102. An insulation film 111 is formed to fill the trench 106 in the thickness direction to a middle height of the control gate FG. Thus, a trench-type device isolation insulating films (STI films) 112 are formed for the floating gate CG to be insulated and isolated from each other. Also, a capacitive insulation film 107 is formed on the floating gate FG, and a control gate film 108 for a control gate CG is formed on the capacitive insulation film 107 and serves as a word line WL extending in the row direction.
FIGS. 2A to 2C show a manufacturing method of the STI films and the memory cells. As shown in FIG. 2A, a tunnel oxide film 102, a floating gate film 103, a buffering oxide film 104, and a nitride film 105 serving as polishing stopper film 105 are sequentially formed on a well WELL in the semiconductor substrate 101. Subsequently, these films and the semiconductor substrate 101 are selectively etched, to form the respective trenches 106 of a predetermined depth. Next, as shown in FIG. 2B, an insulating film 111 is deposited to fill the trenches and to cover the nitride film 105. Subsequently, as shown in FIG. 2C, the insulating film 111 is polished by a chemical mechanical polishing (CMP) method by using the nitride film 105 as a stopper, to flatten the surface of the insulating film 111. Then, the nitride film 105 and the oxide film 104 are etched, and the surface of the insulating film 111 is etched. Thus, the insulating film 111 is remains only in the trenches 106, and the STI film is formed. Subsequently, the capacitive insulating film 107 and the control gate film 108 are formed on the STI film in order, and these films are patterned into a predetermined pattern. Subsequently, impurity is ion-implanted to form the drain regions 109 and the source regions 110. Thus, the STI films 112 and the memory cells M shown in FIGS. 1A and 1B are formed. Such an STI film manufacturing method is disclosed in Japanese Laid Open Patent Application (JP-P2002-110780A).
According to the STI film manufacturing method, as shown in FIG. 2B, there is a case that the certain trench 106 is not completely or sufficiently filled with the insulating film 111 due to foreign substance Z. In such a case, a void V is produced in the trench 106 when the insulating film 111 is polished. Consequently, the capacitive insulating film 107 and a part of the control gate film 108 are formed in subsequent steps, to fill the inside of the trench 106, as shown in FIG. 2C. Thus, the control gate film 108 is formed to oppose to the well WELL of the semiconductor substrate 101 through only the thin capacitive insulating film 107. Specifically, the control gate CG is in contact with the well WELL through only the thin capacitive insulating film 107.
By the way, referring to FIGS. 1A and 1B, and 4, a writing operation into the memory cell of the above-described type will be described. In case of the writing operation, a voltage VCG of the control gate CG is set to a positive voltage of about 9 V, and a voltage VWELL of the semiconductor substrate 101 is set to a GND (ground) potential of 0 V. Also, in case of an erasing operation, a negative voltage VCG of about 9 V is applied to the control gate CG, and a positive voltage VWELL lower than +9 V is applied to the well WELL. Therefore, electric field stress of about 9–18 V as a voltage difference between the control gate voltage VCG and the well voltage VWELL is applied to the capacitive insulating film 107. In case of the semiconductor device in which the trench 106 is appropriately filled with the insulating film 111 serving for the STI film 112, the electric field stress is applied through the insulating film 111 and the capacitive insulating film 107 to the STI film 112. In this case, therefore, the STI film 112 has a sufficient endurance. However, in case of the semiconductor device in which the trench 106 is not sufficiently filled with the insulating film 111, as shown in FIG. 2B, there is only the thin capacitive insulating film 107 between the control gate CG and the well WELL. In this case, therefore, deterioration of the capacitive insulating film 107 advances when the electric field stress is repeatedly applied. Finally, electrical leakage or breakdown X occurs between the control gate CG and the well WELL, and causes a memory operation fault.
In order to prevent delivery of a semiconductor device having a possible operation fault, it is preferable to carry out a test where the writing/erasing operations are repeated. However, such a test method requires a long test time. Also, if the number of times of the writing/erasing operations is not appropriate, there is a possibility that a semiconductor device having the possible operation fault may be delivered. In such a case, deterioration of the capacitive insulating film could further advance through a final product test and the actual use of the semiconductor device by an end user, resulting in the semiconductor device being regarded as a defective product. As a result, reliability of the manufacturer side will be lost.